Pre-lab

Prior to coming into your assigned lab section, you must read through and understand this pre-lab document, which details a handshake-based, ready-valid interface protocol for transmitting data from one component of a design (source) to another (sink).

Check your understanding

Discuss with your partner:

Module A (Source) has valid data available, and Module B (Sink) is ready to receive it. Describe the state of the three main signals (Data, Valid, Ready) in the FIFO Interface during the cycle just before data is transferred to the Sink.

If you have any questions about the FIFO buffer, please ask a TA. You need a solid understanding of the FIFO buffer before moving on to writing assertions.