Overview

This lab will help you grow your assertion-based verification knowledge and develop skills like FSM comprehension and assertion writing. Assertion-based verification is an increasingly important step in hardware design, and industry is paying attention. We hope that this assignment will equip you with skills needed to pursue a successful career in hardware verification. In this lab, you will write SystemVerilog Assertions to functionally verify the FIFO buffer shown in Figure 8 of the pre-lab document (copied below for your convenience).

FIFO diagram

Parts

Both partners will read the Pre-Lab (if you didn’t already read it), answer the associated concept check, and read through the Introduction. Then, you will split up. Partner A writes assertions for the Moore FSM of the FIFO buffer, and Partner B for the Mealy FSM. Finally, you will come together for the discussion. Once you are done, a TA will come to check you off.